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DM93S62 9-Input Parity Checker/Generator
October 1988 Revised May 2000
DM93S62 9-Input Parity Checker/Generator
General Description
The DM93S62 is a very high speed 9-input parity checker/ generator for use in error detection and error correction applications. The DM93S62 provides odd and even parity for up to nine data bits. The even parity output (PE) is HIGH if an even number of inputs are HIGH and E is LOW. The odd parity output (PO) will be HIGH if an odd number of inputs are HIGH and E is LOW. A HIGH level on the Enable (E) input forces both outputs LOW.
Ordering Code:
Order Number DM93S62N Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Logic Symbol
Connection Diagram
VCC = Pin 14 GND = Pin 7
Pin Descriptions
Pin Name I0-I8 E PO PE Data Inputs Output Enable (Active LOW) Odd Parity Output Even Parity Output Description
Truth Table
(E = LOW) Number of Inputs I0-I8 that are HIGH 1, 3, 5, 7, 9 0, 2, 4, 6, 8
H = HIGH Voltage Level L = LOW Voltage Level
Outputs PO H L PE L H
(c) 2000 Fairchild Semiconductor Corporation
DS009809
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DM93S62
Functional Description
The DM93S62 is a very high speed 9-input parity checker or generator. It is intended primarily for error detection in systems which transmit data in 8-bit bytes, but it can be expanded to any number of data inputs. Both even and odd parity outputs are available to allow maximum flexibility for both parity generation and parity checking. When the device is enabled (E = LOW), the Even Parity output (PE) is HIGH when an even number of inputs is HIGH, and the Odd Parity output (PO) is HIGH when an odd number of inputs is HIGH. The active LOW Enable (E) controls the state of both outputs; when the Enable (E) is HIGH, both outputs will be LOW. The Enable may be used to strobe the outputs at very high speeds to synchronize or inhibit the parity data. The DM93S62 has been designed with two sections using Exclusive-NOR comparison techniques. Eight data inputs I0-I7 represent one section which will generate a parity bit in 16 ns to 20 ns. The ninth input (I8) bypasses three levels of logic and switches the outputs in 6.0 ns to 9.0 ns. This feature may be used to compensate for delayed arrival of the parity bit, allowing faster system cycle times (Figure 1). The fast I8 input is also useful when more than nine bits are to be checked. The output of one DM93S62 drives the I8 input of a second DM93S62, providing a 17-bit parity check in 29 ns (typ). When some inputs of the DM93S62 are not used, such as for words of less than nine bits or when using parallel expansion techniques, there is an optimum delay scheme for termination of the unused inputs (see Table 1). In essence, if one of the inputs of any Exclusive-NOR stays HIGH, the delay from the other input to the output is minimized.
TABLE 1. Termination Recommendations for Less than Nine Bits Number of Data Inputs 3 4 5 6 7 8 D0 D0 D0 D0 D0 D0 L L L D1 D1 D1 D1 D1 D1 D2 D2 D2 L L L D3 D3 D3 D2 D2 D2 D4 D4 D4 L L L L L D5 L D3 D3 D5 D5 D6 L L L L L D7 L L D4 L D6 L I0 I1 I2 I3 I4 I5 I6 I7 I8
FIGURE 1. Fast Input I8 allows Higher System Speed
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DM93S62
Logic Diagram
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DM93S62
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL TA Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature 0 Parameter Min 4.75 2 0.8 -1 20 70 Nom 5 Max 5.25 Units V V V mA mA C
Electrical Characteristics
Over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL II IIH IIL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max VCC = Min, IOL = Max VIH = Min VCC = Max, VI = 5.5V VCC = Max, VI = 2.7V VCC = Max, VI = 0.5V, I0-I8 VCC = Max, VI = 0.5V, E Only IOS ICC Short Circuit Output Current Supply Current VCC = Max (Note 3) VCC = Max -40 2.7 3.4 0.35 0.5 1 50 -1.6 -3.2 -100 65 Min Typ (Note 2) Max -1.2 Units V V V mA A mA mA mA
Note 2: All typicals are at VCC = 5V, TA = 25C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
VCC = +5.0V, TA = +25C Symbol tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay I0-I7 to PE Propagation Delay I8 to PE Propagation Delay I0-I7 to PO Propagation Delay I8 to PO Propagation Delay E to PE Propagation Delay E to PO Parameter CL = 15 pF Min Max 26 22 12 9.0 26 26 13 13 7.0 7.0 7.0 7.0 Units ns ns ns ns ns ns
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DM93S62 9-Input Parity Checker/Generator
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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